The present invention relates to semiconductor device and fabrication process thereof, and more particularly to a semiconductor device having a metal thin-film resistance element formed of a metal thin-film, which in turn is formed on an insulation film.
Resistance elements constitute an important part of an analog integrated circuit.
Particularly, a resistance element of a metal thin-film (called hereinafter as metal thin-film resistance) attracts attention in view of its small temperature dependence of the resistance value (TCR).
For the material of such metal thin-film resistance, chromium-silicon (CrSi), nickel chromium (NiCr), tantalum nitride (TaN), chromium silicide (CrSi2), chromium silicide nitride (CrSiN), chromium silicon oxy (CrSiO), and the like, are used.
With a semiconductor device having such a metal thin-film resistance, it is generally practiced to form the metal thin-film resistance with a very small thickness of 1000 Angstroms or less in order to meet for the demand of high integration density and for higher sheet resistance.
Conventionally, following methods are known for achieving electrical connect with a metal thin-film resistance:
1) Directly connecting a metal interconnection pattern to the metal thin-film resistance (Patent Reference 1);
2) Forming an interlayer insulation film after formation of the metal thin-film resistance; forming a contact hole in the interlayer insulation film; and connect a metal interconnection via the foregoing contact hole (Patent Reference 2 and Patent Reference 3).
3) Forming a barrier layer on the metal thin-film resistance and connecting a metal interconnection to such a barrier film (Patent Reference 4 and Patent Reference 5); and
4) Forming an electrode in a contact hole formed in an insulation film, forming a resistance film on the insulation film, and forming a pattern of the resistance body by applying an anisotropic etching process to the resistance film such that the resistance pattern makes a contact with the electrode (Patent Reference 1).
Hereinafter, the method of achieving electrical connection to the metal thin-film resistance of the prior art 1)-4) above will be explained.
First, the method 1) of forming a metal interconnection directly on a metal thin-film resistance will be explained with reference to FIGS. 22A-22F.
(1) Referring to FIG. 22A, a BPSG (borophospho-silicate film) film 5 is formed on a silicon substrate 1 still having the form of wafer, on which a device isolation oxide film 3 and active devices such as transistors are formed, as a first interlayer insulation film 5 located between the gate electrode of the transistors and a metal interconnection pattern. Further, a reflowing processing, and the like, is conducted.
(2) Next, in the step of FIG. 22B, a metal thin-film 73 used for the metal thin-film resistance is formed on the entire surface of the silicon substrate 1 with the thickness of 20-500 Angstroms.
Further, in the step of FIG. 22C, there is formed a resist pattern 75 on the metal then film 73 so as to define the region in which the metal thin-film resistance is to be formed, followed by a patterning process of the metal thin-film 73 while using the resist pattern 75 as a mask, to form a metal thin-film resistance 77.
(4) After removing the resist pattern 75, a metal film 79 of an AlSiCu alloy used for the interconnection pattern is formed on the entire surface of the first interlayer insulation film 5 including the metal thin-film resistance 77 as represented in FIG. 22D. Further, there is formed a resist pattern 81 on the metal film 79 for patterning the same such that the interconnection metal film 79 remains at both end parts of the metal thin-film resistance 77.
(5) Further, in the step of FIG. 22E, the interconnection metal film 79 is patterned while using the resist pattern 81 as a mask, to form a metal interconnection pattern 83. Thereby, it should be noted that, in the general fabrication process of semiconductor devices, a dry etching technology will be used in the etching process of such an interconnection metal film 79, while in the present case in which there exists a very thin metal thin-film resistance 77 underneath the interconnection metal film 79, there arises a problem that the metal thin-film resistance 77 may be etched at the time of the overetching process when a dry etching process is used. Thus, it is not possible to use a dry etching process in the foregoing process of FIG. 22E, and the interconnection metal film 79 has to be patterned by using a wet etching process.
(6) Further, by removing the resist pattern 81 in the step of FIG. 22F, formation of the metal thin-film resistance 77 having the metal interconnection patterns 83 connected to the metal thin-film resistance 77 is completed.
Next, the method 2) of forming the interlayer insulation film after formation of the metal thin-film resistance, forming the contact hole in the interlayer insulation film, and connecting a metal interconnection pattern via the contact hole, will be explained with reference to FIGS. 23A-23F.
(1) Similarly to the steps (1)-(3) explained previously with reference to FIGS. 22A-22C, there are formed a device isolation oxide film 3, a first interlayer insulation film 5 and a metal thin-film resistance on a silicon substrate in the step of FIG. 23A.
(2) Next, in the step of FIG. 23B, there is formed a CVD (chemical vapor deposition) oxide film 85 on the first interlayer insulation film 5 including the metal thin-film resistance 77 as an interlayer insulation film for the metal interconnection with the thickness of about 2000 Angstroms.
(3) Next, in the step of FIG. 23C, there is formed a resist pattern 87 having an opening in correspondence to respective ends of the metal thin-film resistance 77 on the CVD oxide film 85 for the formation of the contact holes for the metal interconnection patterns. Further, by using the resist pattern 87 as a mask, the CVD oxide film 85 is subjected to a wet etching process to form contact holes 89. Here, it should be noted that, in the general fabrication process of semiconductor devices, a dry etching technology will be used in the etching process for formation of the contact holes 89, while in the present case in which there exists a very thin metal thin-film resistance 77 having the thickness of 1000 Angstroms or less, it is difficult to prevent the problem of the contact holes 89 penetrating through the metal thin-film resistance 77 with such a dry etching process, and it is necessary to use a wet etching process for forming the contact holes 89.
(4) Next, in the step of FIG. 23D, an interconnection metal film of an AlSiCu alloy is formed on the CVD oxide film 85 including the interior of the contact holes 89.
(5) Next, in the step of FIG. 23E, a resist pattern 93 is formed on the interconnection metal film 91 for patterning the interconnection metal film 91 such that the interconnection metal film remains at both ends of the metal thin-film resistance 77.
(6) Further, a dry etching process is applied in the step of FIG. 23F to pattern the interconnection metal film 91 while using the resist pattern 93 as a mask, to form metal interconnection patterns 95. In this dry etching process, there arises no problem that the metal thin-film resistance 77 is etched even when a dry etching process is used because of the existence of the CVD oxide film 85 underneath the interconnection metal film 91. After removal of the resist pattern 93, formation of the metal interconnection pattern 95 for electrical interconnection between the metal thin-film resistance 77 and the metal interconnection pattern 95 is completed.
Next, the method 3) of forming a barrier film on the metal thin-film resistance and connecting a metal interconnection to such a barrier film will be described with reference to FIGS. 24A-24E.
(1) Similarly to the steps (1)-(3) explained with reference to FIGS. 22A-22C, the device isolation oxide film 3, the first interlayer insulation film 5 and the metal thin-film resistance 77 are formed on the silicon substrate in the step of FIG. 24A.
(2) Next, in the step of FIG. 24B, a refractory metal film 97 of TiW, or the like, is formed on the first interlayer insulation film 5 including the metal thin-film resistance 77 as the barrier film of the metal interconnection, and an interconnection metal film 99 of an AlSi or AlSiCu alloy is formed further thereon.
(3) Next, in the step of FIG. 24C, there is formed a resist pattern 101 on the interconnection metal film 99 for patterning the interconnection metal film 99 such that the interconnection metal film 99 remains at both lateral ends of the metal thin-film resistance 77.
(4) Further, while using the resist pattern 101 as a mask, the interconnection metal film 99 is patterned by a dry etching process to form a metal interconnection pattern 103 as shown n FIG. 24D. In this process, there is no risk of the metal thin-film resistance 77 being etched even when the etching is conducted by a dry etching process because of the existence of the refractory metal film 97 underneath the interconnection metal film 99.
(5) Next, in the step of FIG. 24E, the resist pattern 101 is removed and the refractory metal film 97 is removed selectively by a wet etching process while using the metal interconnection pattern 103 as a mask, to form a refractory metal film pattern 105. With this, formation of the metal thin-film resistance body 77, the metal interconnection pattern 103 in electrical connection with the metal thin-film interconnection body 77 and the refractory metal film pattern 105 is completed. Here, it should be noted that, because the refractory metal film 97 is provided immediately on the metal thin-film resistance 77, patterning of the refractory metal film 97 by a dry etching process is difficult.
Next, the method 4) of forming an electrode in a contact hole formed in an insulation film and then forming a resistance pattern by an anisotropic etching process of a resist film formed on the insulation film such that the resistance pattern is connected to the electrode, will be explained with reference to FIGS. 25A-25E. Here, explanation will be made for the case of forming a metal interconnection pattern further on the metal interconnection pattern formed underneath the contact hole.
(1) Referring to FIG. 25A, there is formed a BPSG film on a silicon substrate still in the form of wafer on which formation of a device isolation oxide film 3 and transistors (not illustrated) is completed, as a first interlayer insulation film between the gate electrode of the transistor and the metal interconnection pattern. Further, reflowing is conducted and a metal interconnection pattern 107 is formed on the first interlayer insulation film 5. On the first interlayer insulation film 5, there is formed an insulation film 109, and after planarization of the top surface of the insulation film 109, there are formed first contact holes 111 in the insulation film 109 in the parts thereon located on the metal interconnection patterns 107 disposed at both ends of the metal thin-film resistance. Here, it should be noted that there is formed no contact hole for connecting the metal interconnection patterns 107 with the upper layer metal interconnection patterns to be formed later by a latter process. Thereafter, the first contact holes 111 are filled with a conductive material and there formed first conductive plugs 113.
(2) Next, in the step of FIG. 25B, a metal thin-film is provided on the entire surface of the insulation film 109 for formation of the metal thin-film resistance, wherein the metal film thus formed is patterned to form the metal-thin film resistance 77 by conducting an anisotropic etching process while using a resist pattern formed on the foregoing metal thin-film for defining the region where the metal thin-film resistance is to be formed, as a mask.
(3) Next, in the step of FIG. 25C, an insulation film 115 is formed on the entire surface of the insulation film 109 so as to include the formation region of the metal thin-film resistance 77, wherein it should be noted that this insulation film 115 is formed for the purpose of preventing the etching of the metal thin-film resistance 77 at the time of the anisotropic etching process for patterning the upper metal interconnection pattern formed by the later process. It should be noted that the insulation film 109 and the insulation film 115 constitute a second interlayer insulation film.
(4) Next, in the step of FIG. 25D, there is formed a second contact hole 117 in the insulation films 109 and 115 on the metal interconnection pattern 107 in the region different from the region in which the metal thin-film resistance 77 is formed, for the purpose of electrical connection with the foregoing upper metal interconnection pattern. Thereafter, the second contact hole 117 is filled with the conductive material and the second conductive plug 119 is formed.
(5) Next, in the step of FIG. 25E, a metal film for the upper metal interconnection pattern is formed on the insulation film 115 including the region where the second conductive plug 119 is formed, and an upper metal interconnection pattern 121 is formed as a result of patterning conducted by a photolithographic process and an anisotropic etching process such that the metal interconnection pattern 121 covers a predetermined region of the insulation film including the region where the second conductive plug 119 is formed. In this process, it should be noted that etching of the metal thin-film resistance 77 is prevented by the insulation film 115 covering the metal thin-film insulation film 77.
Further, there is a proposal of a semiconductor integrated circuit device for example in Patent Reference 6, in which there is formed a resistance body (not a metal thin-film resistance) on an insulation film covering an uppermost interconnection electrode in electrical connection with such an uppermost interconnection electrode.
Hereinafter, the method will be explained in which such a structure is applied to a metal thin-film resistance with reference to FIGS. 26A-26D.
(1) Referring to FIG. 26A, a BPSG film 5 is formed on a silicon substrate 1 still in the form of wafer on which a device isolation oxide film 3 and transistors (not shown) are formed, as a first interlayer insulation film located between the gate electrode of the transistor and a metal interconnection pattern. Thereafter, a reflowing process is conducted, and there are further formed a metal interconnection pattern 107 and a second interlayer insulation film 123 on the first interlayer insulation film 5, wherein the second interlayer insulation film 123 is formed consecutively of a CVD oxide film, an SOG (spin-on-glass) film formed on the CVD oxide film and another CVD oxide film formed on the SOG film. In FIGS. 26A-26D, it should be noted that the lower CVD oxide film, the SOG film and the upper CVD oxide film are represented collectively as the second interlayer insulation film 123.
(2) Next, in the step of FIG. 26B, there is formed a resist pattern 125 for defining the region for a contact hole in the second interlayer insulation film 123.
(3) Next, in the step of FIG. 26C, the second interlayer insulation film 123 is selectively removed while using the resist pattern 125 as a mask, and with this, there is formed a contact hole 127 in the second interlayer insulation film 123 on the metal interconnection pattern 107. Here, it should be noted that a part at the upper side of the metal interconnection pattern 107 is removed as a result of the overetching.
(4) Next, in the step of FIG. 26D, there is formed a metal thin-film 129 for the metal thin-film resistance on the entire surface of the second interlayer insulation film 123 including the region where the contact hole 127 is formed, with the thickness of 20-500 Angstroms. Thereafter, the metal thin-film 129 is patterned to form the metal thin-film resistance having a predetermined shape.
Further, there is a proposal of a semiconductor device having a metal thin-film resistance in the form of a semiconductor integrated circuit that carries the metal thin-film resistance on an insulation film as set forth in Patent Reference 7, for example, in which contact is achieved between the electrode part of the metal thin-film resistance and the metal interconnection pattern at an edge part or at least a part of the top surface of the metal interconnection pattern.
References
                Patent Reference 1 Japanese Laid-Open Patent Application 2002-124639 Official Gazette        Patent Reference 2 Japanese Laid-Open Patent Application 2002-261237 Official Gazette        Patent Reference 3 Japanese Patent 2,699,559        Patent Reference 4 Japanese Patent 2,932,940        Patent Reference 5 Japanese Patent 3,185,677        Patent Reference 6 Japanese Laid-Open Patent Application 58-148443 Official Gazette        Patent Reference 7 Japanese Laid-Open Patent Application 61-100956 Official Gazette        